ATHENS, Greece -- Alma Technologies S.A. announces the addition of three new Ultra High Throughput H.264 encoders to its UHT Image & Video Compression IP product line.
This new family of scalable H.264 encoders offers progressively increasing levels of compression and enables 4K resolutions in power- and cost-effective FPGA and ASIC implementations. Each of the three new H.264 encoders can be configured to support Baseline, Main and High profiles, 4:2:0 and 4:2:2 chroma sampling, and up to 12-bit per component color depth. All can be also used for high frame rate SD to Full HD interlaced or progressive video encoding.
Compared to the other H.264 IP cores available by Alma Technologies, these new UHT H.264 encoders have been designed to support UHD resolutions in a much broader range of silicon speed options. They continue to offer the same advanced feature set, including the perceptually optimized image quality and the low-latency Intra and Intra-Refresh encoding modes. They also continue to offer different levels of compression efficiency, ensuring an efficient matching between custom requirements sets and the corresponding silicon area and power figures of the implementation:
•The first new member of the UHT IP product line is the UHT-H264E-IDR core. This is an Intra frames only encoder and has the smallest silicon footprint of the three. This encoder is suitable for applications requiring high video quality in relatively low compression ratio working range.
•The next addition is the UHT-H264E-LME encoder which is equipped with a very compact Light Motion Estimation engine. This core best suits area critical applications that need a medium level of compression or work with video content that has low motion complexity.
•The third new member is the UHT-H264E-FME. Powered by a highly featured Full Motion Estimation engine, this encoder offers best-in-class compression for applications needing advanced H.264 efficiency for high-quality low bitrate video encoding.
The new UHT H.264 encoders are based on a scalable architecture that uses a configurable number of internal, parallel processing, engines. This is done in a way which is totally transparent to the system utilizing the IP, abstracting all the parallelization complexity from the rest SoC design and operation. In addition to the configurable number of internal engines that matches the throughput requirements to the available silicon speed, each encoder can be further fine-tuned before synthesis to save silicon area by removing features that are not needed in a certain implementation.
The Alma Technologies UHT H.264 encoders are very easy-to-use and integrate in a system. They are autonomous, CPU-less, complete H/W implementations, accepting video input in standard raster scanned interleaved pixel order and producing ready-to-use H.264 NAL byte-stream output.
Learn more at http://www.alma-technologies.com