This article describes how to sample a signal more quickly and efficiently by using a method of heterodyning (generating new frequencies by mixing or multiplying two oscillating waveforms) over the frequency range of interest. The advantages are that this selective sampling method retains the same frequency resolution as obtained in standard pulse-code modulation (PCM) designs but with a shorter sampling time. In particular, the article shows how to use such a method to detect transient power changes more rapidly.

**Time Domain Sampling**

Time domain sampling uses an analog-to-digital converter (ADC) that samples an analog signal to convert it to digital format. The sampling frequency of the ADC is chosen to be at least twice the highest frequency in the signal, as the Nyquist theorem requires this to insure that aliasing, or artifacts, are not created. To achieve this, an anti-aliasing filter is placed between the signal and the ADC to attenuate signals that are more than one half the sampling frequency of the ADC.

For example, we will examine a system that samples a signal in the frequency range of 6000–8000 Hz with a desired frequency resolution of 0.5 Hz. Normally, we would sample this signal at 16,000 Hz to satisfy the Nyquist criteria; to achieve 0.5 Hz resolution we would take 32,000 samples (N=32,000, where N is the number of samples), which would typically require 2 s at a 16,000 Hz sampling frequency. Using the proposed method, it is possible to significantly reduce the sampling time to 0.576 s.

**Selective Sampling**

In **Figure 1** the incoming signal to be sampled is filtered with a band-pass filter for anti-aliasing. The filter has cut-off frequencies of *F _{L}* = 6000 Hz and

*F*= 8000 Hz, where

_{H}*F*and

_{L}*F*are, respectively, the low and high cut-off frequencies. The filtered signal is then sent to two independent multipliers where it is multiplied with synthesized signals from two digital-to-analog converters (DACs). Two more ADCs sample the outputs of the multipliers at a sampling frequency of 4

_{H}*F*. The two separate sets of sampling circuitry are required to find the phase and amplitude components in the spectrum. With twice as many equations that result from two sets of ADC measurements, both phase and amplitude components can be solved simultaneously.

_{H}

Figure 1. Design for a selective sampler |

The synthesized signal from the DACs in Figure 1 is a series of sine waves that sweep from 6000–8000 Hz in 0.5 Hz increments, with four points of sampling for each sine wave being synthesized (hence the four-times sampling on the ADC). Each sine wave is synthesized for the maximum period of all frequencies being sampled, which in this case is the period of a 6000 Hz sine wave. The multipliers in Figure 1 perform the operation shown in **Equation 1** when sine wave 1 is directed to one input and sine wave 2 is directed to the other input:

(1) |

where:

A_{1} | = | amplitude of sine wave 1 |

F_{1} | = | frequency of sine wave 1 |

A_{2} | = | amplitude of sine wave 2 |

F_{2} | = | frequency of sine wave 2 |

From the trigonometric identity for the multiplication of sine functions [1] shown in **Equation 2:**

(2) |

we obtain the relationship shown in **Equation 3**:

(3) |

For each sine wave of sample *n*, synthesized by the DAC at 0.5 Hz increments, the multiplier output is given by substituting *F _{1}* =

*F*and

_{dn}*F*=

_{2}*F*in

_{sn}**Equation 4**:

(4) |

where:

A_{dn} | = | amplitude of each sine wave synthesized by the DACs for time t and sample n |

A_{sn} | = | amplitude of each sample n from the input signal |

F_{dn} | = | frequency synthesized by the DACs for time t and sample n |

F_{sn} | = | frequency of each input sample n from the input signal |

As can be seen from Equations 3 and 4, the familiar sum and difference frequencies appear at the output of the multiplier when sine waves are directed to the inputs. Each synthesized point from the DAC creates part of the sine wave that is multiplied against the Fourier components of the input signal. Each output from the multiplier that corresponds to a synthesized data point from the DAC is read by the ADC and used as a known value to solve a simultaneous set of equations for the input signal's Fourier amplitude and phase. The number of points on the DAC-synthesized sine wave determines how many equations are produced that are patterned after Equation 3 and therefore how many amplitude and phase components can be solved for simultaneously. Where the phase is constant or zero, the equations produced are linear and solvable by inverting the matrix of known values (the time base and synthesized frequencies in Equation 3 are known because they are generated by the microcontroller—only the amplitudes are unknown). This allows us to solve for the amplitude components of the input signal.

In the case of non-zero phase differences between the Fourier components of the input signal and the DAC-synthesized signal, there is a nonlinearity introduced by the cosine of the phase-angle component multiplied by the amplitude component of the same frequency. As this phase component is an unknown variable that is multiplied by the corresponding amplitude component, which is also unknown, we need two sampling systems to generate the required number of equations to solve for the phase and amplitude components of the spectrum. The two sampling systems will simultaneously synthesize sine waves at the same frequency but these sine waves are synthesized at different phase shifts. This creates linearly independent results that can be used to solve for the phase and amplitude of the input signal.

The microcontroller in Figure 1 generates the digital signal for the DAC so that the sweep frequencies *F _{dn}* may be synthesized. The microcontroller also acquires

*n*samples from the output of the multiplier, allowing the microcontroller to perform matrix inversions and the operations necessary to solve the equations. After the DAC synthesizes all frequencies that are to be sampled in the signal and each Fourier component is stored in memory, a complete magnitude spectrum of the sampled signal is available in the memory of the microcontroller for real-time use.

The amount of time required to synthesize all frequencies being sampled in the signal is found from **Equation 5** to be:

(5) |

where:

F | = | the synthesized DAC frequency of 6000–8000 Hz in 0.5 Hz increments |

Equation 5 can also be approximated by dividing the number of samples N by 6000 Hz. In our example, N = [(8000 Hz – 6000 Hz)/(0.5 Hz)] + 1 = 4001 samples, including the beginning frequency of 6000 Hz. This approximation comes out to be 0.67 s. The normal sampling time of 2 s required to obtain this spectrum has been reduced to 0.67 s (not including the time to solve equations, which is considered to be in the microseconds for current digital hardware). Increased accuracy can be obtained by increasing the number of samples in each sine wave synthesized by the DAC from the 4 samples shown in Figure 1 to *P* samples, where *P* > 4.

Although we used *P* = 4 in this example for simplicity, to obtain the 0.5 Hz frequency resolution in our example we would require *P* = (8000 Hz/0.5 Hz) = 16,000 data points/sine wave. Therefore, *P* is the sampling frequency of the ADCs and DACs. An increase in sampling frequency requires either a faster microcontroller or the use of a high-speed FPGA, of which many are available.

**When to Use This Technique**

To determine whether this technique offers an advantage over FFT analysis or other tracking methods, it is necessary to determine the frequency range and resolution required for the application and then to find what reduction is possible in the traditional sampling time.

A useful example is a real-time power monitor/controller for the 60 Hz power grid in North America where a deviation in frequency of 5 Hz/s is an indication that a major instability is occurring [2]. It takes time to build up enough samples with standard sampling to determine a slight change in the 60 Hz frequency. For example, to see a 0.1 Hz change from 60 Hz to 59.9 Hz or 60.1 Hz normally requires 10 s of sampling the power line.

Although this does not seem to be a large change in frequency, a power company's frequency-sensitive relays are designed to shed 15% of the current load if the frequency drops from 60 Hz to 59.3 Hz and it will shed this load in less than 1 s once it detects the frequency change [2]. It is therefore an advantage for the power utility customer to be able to see small frequency changes and to get some advance warning that the power may be disconnected so that the power producer can balance the power network. This gives the customer a small amount of time to prepare by storing data on computers or safely shutting down appliances. The method proposed will allow the detection of a 60 Hz signal changing anywhere from 58 Hz to 62 Hz in 0.1 Hz increments within 0.7 s. This quicker response time allows backup systems to store information and to respond in an emergency.

This article explains how to quickly determine the frequency resolution of a power monitoring system so that load changes, which are represented by small changes in the 59.94 Hz power signal, can be detected prior to blackouts.

**REFERENCES**

1. *Elements of Signals and Systems*, Poularikas and Seely, PWS-KENT, 1988. p. 559

2. *Electrical Power Technology*, Theodore Wildi, John Wiley and Sons, 1981. p. 569

**ABOUT THE AUTHOR**

**Michael Harney** is an Electrical Engineer working in industrial and vehicle electronics. He is the holder of four patents and has a BSEE from Utah State University. He can be reached at Signal Display Systems, Pleasant Grove, UT; 801-628-3476, [email protected].